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Exploring Innovation | ISSN:2319–6378(Online)| Reg. No.:68120/BPL/CE/12 | Published by BEIESP | Impact Factor:4.72
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Volume-2 Issue-10: Published on August 25, 2014
24
Volume-2 Issue-10: Published on August 25, 2014

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S. No

Volume-2 Issue-10, August 2014, ISSN:  2319–6378 (Online)
Published By: Blue Eyes Intelligence Engineering & Sciences Publication Pvt. Ltd. 

Page No.

1.

Authors:

Attrams Siaw Prince, Osei-Owusu Alexander, Yankey-Antwi Aaron

Paper Title:

Powerline Communication System for Controlling Appliances in Ghanaian Homes

Abstract: The deployment of PLC systems have evolved rapidly over the years with the advent of soaring research and improvement, huge strides have been attained in this sector. The use of such technology especially in developing countries like Ghana require the design and implementation of basic systems that can form the basis for further improvements and subsequently meet the pace of modern systems and designs. The research is aimed at designing and constructing a power line communications system that will interface with a simple computer system to control the lightning system in a typical Ghanaian home. The system will allow a centralized point for controlling all the lightning systems within the household. This is in an effort to providing easy control of the lightning system in a household. The design and construction of the system is presented, with added interfacing functionalities such as voice recognition, text messaging, keyboard and the use of the internet via a network socket to send appropriate signals to the system’s receiver.

Keywords:
PLC (Power Line Communication), FDM (Frequency Division Multiplexing), DTMF (Dual Tone Multi Frequency), Control.


References:

1.       GridCo 2009, accessed on 13/ 10/2013 <http://www.gridcogh.com/site/ng.php>.
2.       Australian Communication Authority, Document SP11/03, “Broadband Power Communication Systems”, Australia, September, 2003.

3.       Echelon Corporation 2013, accessed on 17/07/2014 < http://www.echelon.com/applications/>

4.       Wicomb, L.P (2005), ‘OFDM Modulation Techniques for Domestic Powerline Communication’ Cape Peninsula University of Technology, MTech Thesis, accessed 15 July 2014, from the Cape Peninsula University of Technology Database.

5.       Khan Et.al (2006), Communication System for Controlling Smart Appliances Using Powerline Communication Malaysia, IEEE, 2006.

6.       Osama Bilal, Er Liu, Yangpo Gao and. Timo O. Korhonen. DESIGN OF BROADBAND COUPLING CIRCUITS FOR POWERLINE, Finland, Helsinki University of Technology, n.d.

7.       Versolatto, Fabio. Analysis of the PLC Channel Statistics Using a Bottom-Up Random Simulator. Italy, IEEE, 2010.

8.       SunPlus Technology 2013, accessed on 13/10/2013 <http://mcu.sunplusmcu.com/applications/DC_Inverter_Air_Condition.asp>.

9.       John Jay Dernovsek, Deepak Shet Brett Bell. "Digital Control of Electronic Ballast Using AC Power Lines as Communication Medium." Patent. 2005.

10.    Pooja Dave. "POWER LINE COMMUNICATION IN ENERGY MARKETS." Fernandes, Antonio De Lima. Cypress Semiconductor Corp, n.d.


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2.

Authors:

Prasad V. Bapat, S. Magbul Hussain

Paper Title:

Design of Special Purpose Machine Head to Improve the Production of Engine Block

Abstract:  Special purpose machine tools are designed and manufactured for specific jobs and such never producedin bulk such machines are finding increasing use in industries the techniques for designing such machine would obviously be quite different from those used for mass produced machine. A very keen judgment is essential for success of such machines. A special purpose machine was designed and manufactured at ABC Company which found beneficial in increasing production quantity & reducing manpower.

Keywords:
SPM, LOCUS CLEARANCE, MACHINE HEAD,CASTINGS BLOCKS


References:

Internet:
1.             Majid Tolouei-Rad School of Engineering, Edith Cowan
2.             University, Perth “Intelligent Analysis of Utilization of Special
3.             Purpose Machines for Drilling Operations”
4.             www.skf.com/group/...units.../basic-load-ratings/index.html www.bearingworks.com/technical_data/load_ratings.php
Books
5.             Machine Tool Design Handbook: Central Machine Tool Institute, Bangalore. (Tata McGraw-Hill Publishing Company Ltd. Year 2002)
6.             Design of Machine Elements: V. B. Bhandari (Tata McGraw-Hill Publishing Company Ltd. Year 2002)
7.             Machine Design: R.S. Khurmi & J.K. Gupta

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3.

Authors:

Sambit Kumar Patra, Ishita Gupta, Gaurav Saini, Vinodkumar Poolothvalappil

Paper Title:

Data Visualization for Hybrid Application: The challenges in choosing an optimal library for Line Chart

Abstract:   Developing application using web-technology for cross-platform becomes trend these days. However representing data into a small space is more challenging. Digital convergence has led to a sudden dependence on the mobile devices. The data visualization on mobile devices needs to be in a very pristine manner. To achieve that, unique methods are looked upon that generally involve simple but effective presentation instruments such as tables, charts and graphs. So, the challenge comes in deciding and choosing the right charting library for the hybrid mobile application looking over the cost, functionality, performance, and user experience. This paper has illustrated the challenges faced in implementing line chart in hybrid application using Fusion, HighChart, Rickshaw and D3 chart and will help in deciding the best charting library for the same.

Keywords:
Cross-Platforms, Chart Libraries, Comparison, Data Visualization, Hybrid Application, Line Chart, Fusion, HighChart, D3


References:

1.       B. Shneiderman, “The eye have it: A task by data type taxonomy for information visualizations,” in Visual Languages, 1996.
2.       A guide to choosing the right chart type, Szoka, Kathryn, Professional Communication, IEEE Transactions on Volume: PC-25 , Issue: 2 , Publication Year: 1982 ,Page(s): 98 - 101

3.       Daniel A. Keim, “Information Visualization and Visual Data Mining”, IEEE TRANSACTIONS ON VISUALIZATION AND COMPUTER GRAPHICS, VOL. 7, NO. 1, JANUARY-MARCH 2002

4.       “Use and Misuse of Graphical Representations” http://www.montereyinstitute.org/courses/DevelopmentalMath/COU

5.       “Chart” http://en.wikipedia.org/wiki/Chart

6.       Detecting and visualizing refactorings from software archives, Gorg, C. ; Weissgerber, P. Program Comprehension, 2005. IWPC 2005. Proceedings. 13th International Workshop on  Publication Year: 2005 , Page(s): 205 - 214

7.       “FusionCharts by Features” http://www.fusioncharts.com/explore/features/

8.       “Highcharts” www.highcharts.com/

9.       “Rickshaw is a JavaScript Toolkit for crating interactive time series graphs” http://code.shutterstock.com/rickshaw/

10.    “Data Driven Document” http://d3js.org/


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4.

Authors:

Mohammad Vahid Naiemifard, Seied Ali Hosseini

Paper Title:

High Performance Current-Mode Multiplier Circuit Based on Carbon Nanotube Transistors

Abstract:  Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on CNFET technology shows that the proposed multiplier has better features than CMOS Multiplier. Multiplier-divider circuits is using in digital signal processing base on neural networks and communications (amplifiers with variable gain, modulators, detectors and,…).In Most of CMOS analog circuit, transistors are only in triode or saturate regions; till now both regions not used. In this one kind of current mode multiplier-divider circuits is intrudused.it is very simple, has low die area and wide range in low voltage. All tough this circuit has no sense to temperature variation and varying parameters.

Keywords:
CNT. Analog signal processing, current-mode operation, multiplier, reconfigurable circuits.


References:

1.       R. Harjani, “A low-power CMOS VGA for 50 Mb/s disk drive read channels,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 6, pp. 370–376, Jun. 1995.
2.       Motamed, C. Hwang, and M. Ismail, “A low-voltage low-power wide rang CMOS variable gain amplifier,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 7, pp. 800–811, Jul. 1998.

3.       Popa, Synthesis of Computational Structures for Analog Signal Processing, New York, USA: Springer-Verlag, 2011.

4.       Popa, Superior-Order Curvature-Correction Techniques for Voltage References, New York, USA: Springer-Verlag, 2009.

5.       Popa, “Low-power CMOS bulk-driven weak-inversion accurate current-mode multiplier/divider circuits,” in Proc. Int. Conf. Electr Electron. Eng., 2003, pp. 66–73.

6.       C. Popa, “Computational circuits using bulk-driven MOS devices,” in Proc. IEEE EUROCON Conf., May 2009, pp. 246–251.

7.       C. Popa, “Logarithmic curvature-corrected weak inversion CMOS voltage reference with improved performances,” presented at the 11th Int. Workshop on Thermal Investigations on ICs and Systems, Lake Maggiore, Italy, 2005.

8.       C. Popa, “A new curvature-corrected voltage reference based on the weight difference of gate-source voltages for subthreshold-operated MOS transistors,” in Proc. Int. Symp. Circuits Syst., 2003, pp. 585–588.

9.       C. C. Chang and S. I. Liu, “Weak inversion four-quadrant multiplier and two-quadrant divider,” Electron. Lett., vol. 34, no. 22, pp. 2079–2080, Oct. 1998.

10.    M. Gravati, M. Valle, G. Ferri, N. Guerrini, and N. Reyes, “A novel current-mode very low power analog CMOS four quadrant multiplier,” in Proc. 31st Eur. Solid-State Circuits Conf., Sep. 2005, pp. 495–498.

11.    C. Popa, “High accuracy CMOS multifunctional structure for analog signal processing,” in Proc. Int. Semicond. Conf., 2009, pp. 427–430.

12.    C. Popa, “CMOS multifunctional computational structure with improved performances,” in Proc. 33th Ed. Annu. Semicond. Conf., vol. 2. 2010, pp. 471–474.

13.    C. Popa, “Multiplier circuit with improved linearity using FGMOS transistors,” in Proc. Int. Symp. ELMAR 2009, pp. 159–162.

14.    Y. H. Kim and S. B. Park, “Four-quadrant CMOS analogue multiplier,” Electron. Lett., vol. 28, no. 7, pp. 649–650, Mar. 1992.

15.    Y. K. Seng and S. S. Rofail, “Design and analysis of a +-1 V CMOS four-quadrant analogue multiplier,” IEEE Proc. Circuits, Devices Syst., vol. 145, no. 3, pp. 148–154, Jun. 1998.

16.    C. Sawigun and J. Mahattanakul, “A 1.5V, wide-input range, high bandwidth CMOS four-quadrant analog multiplier,” in Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 2318–2321.

17.    C. Sawigun, A. Demosthenous, and D. Pal, “A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier,” in Proc. 18th Eur. Conf. Circuits Theory Design, Aug. 2007, pp. 751–754.

18.    C. Popa, “Improved linearity active resistor with controllable negative resistance,” in Proc. IEEE Int. Conf. Integr. Circuits Design Technol., Aug. 2006, pp. 1–4.

19.    C. Popa and A. M. Manolescu, “CMOS Differential Structure with Improved Linearity and Increased Frequency Response,” in Proc. Int. Semicond. Conf., vol. 2. Sep.–Oct. 2007, pp. 517–520.

20.    C. Popa, “Programmable CMOS active resistor using computational circuits,” in Proc. Int. Semicond. Conf., Oct. 2008, pp. 389–392.

21.    C. Popa, “Improved linearity CMOS active resistor based on the mirroring of the ohm law,” in Proc. IEEE 17th Int. Conf. Electron., Circuits, Syst., Dec. 2010, pp. 450–453.

22.    Naderi, H. Mojarrad, H. Ghasemzadeh, A. Khoei, and K. Hadidi, “Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed,” in Proc. IEEE EUROCON Conf., May 2009, pp. 282–287.

23.    Naderi, A. Khoei, and K. Hadidi, “High speed, low power four quadrant CMOS current-mode multiplier,” in Proc. IEEE Int. Conf. Electron., Circuits Syst., Dec. 2007, pp. 1308–1311.

24.    M. Manolescu and C. Popa, “A 2.5GHz CMOS mixer with improved linearity,” J. Circuits, Syst. Comput., vol. 20, no. 2, pp. 233–242, 2010.

25.    S. I. Liu and Y. S. Hwang, “CMOS squarer and four-quadrant multiplier,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 42, no. 2, pp. 119–122, Feb. 1995.

26.    S. A. Mahmoud, “Low voltage low power wide range fully differential CMOS four-quadrant analog multiplier,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits Syst., Aug. 2009, pp. 130–133.

27.    C. Sawigun and W. A. Serdijn, “Ultra-low-power, class-AB, CMOS four quadrant current multiplier,” Electron. Lett., vol. 45, no. 10, pp. 483–484, May 2009.


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