8-Bit Radix-4 Booth Multiplier using GDI Technique
Ankita Dhankar1, Satyajit Anand2

1Ankita Dhankar, Electronics and Communication Department, M.Tech. VLSI Design, Mody Institute of Technology and Science, Lakshmangarh, India.
2Satyajit Anand, Electronics and Communication Department, Mody Institute of Technology and Science, Lakshmangarh, India.
Manuscript received on April 11, 2013. | Revised Manuscript Received on April 12, 2013. | Manuscript published on April 25, 2013. | PP: 89-91 | Volume-1, Issue-6, April 2013. | Retrieval Number: E0220031513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: An 8-bit radix-4 Booth Multiplier is implemented that demand high speed and low energy operation. It is a good approach if we implement the multiplier as a hybrid architecture of the radix-4/-8 because the radix-8 mode has low power consumption capability, occupying less area and number of partial products obtained in this mode are less(N/3). But the detection of the 3B term while computing the partial products is very difficult and it is difficult to implement it on the FPGA board. So by comparing the performances of the two multipliers we suggest to go with the radix-4 multiplier. Compared to a conventional CMOS Multiplier, the proposed multiplier’s power delay product is 10% less with the use of only 1656 transistors in comparison to conventional CMOS circuit, which uses 2782 transistors.
Keywords: Cncoder, multiplier, gate-diffusion input (GDI), power consumption, PPG