Hardware Implementation of Virtual Reconfigurable Circuit for Fault Tolerant Evolvable Hardware System on FPGA
Omar E. Elnokity1, Imbaby I. Mahmoud2, Mohamed K. Refai3, Hasan M. Farahat4
1Omar E. Elnokity, Department of System & Computer, Alazhar University, Faculty of Engineering, Cairo, Egypt.
2Imbaby I. Mahmoud, Department of Engineering and Scientific Institute, Atomic Energy Authority of Egypt, Nuclear Research Center, Inshas, Egypt.
3Mohamed K. Refai, Department of System & Computer, Alazhar University, Faculty of Engineering, Cairo, Egypt.
4Hasan M. Farahat, Department of System & Computer, Alazhar University, Faculty of Engineering, Cairo, Egypt.
Manuscript received on October 15, 2014. | Revised Manuscript received on October 22, 2014. | Manuscript published on October 25, 2014. | PP:7-10 | Volume-2 Issue-12, October 2014. | Retrieval Number: L08251021214/2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This research verify and describes a Virtual Reconfigurable Circuit (VRC) that designed and implemented for a Fault Tolerant Evolvable Hardware (EHW) system used to calculate the thermal power output of Egypt’s second Training and Research Reactor (ETRR2) during operation. This circuit have three measured input signals from the reactor core: inlet temperature Tin, outlet temperature Tout, mass flow rate Q, and one output, which is the calculated thermal power. In any time the true thermal power reading should be available even one input signal get lost due to a problem in its transducer, or wire cutting, …etc. Typically, this is the function of that Fault Tolerant EHW system. The VRC design will implemented over ordinary Field Programmable Gate Array (FPGA) chip. Reducing the FPGA’s configuration bits length++ is the main advantage of using VRC. Most VRCs done before used logic based function elements, while in this work, an arithmetic based elements are used, to accommodate the application nature. The design is fully synthesized on ALTERA Cyclone IV GX Family, and the design gave promising results when targeted to the EP4CGX30CF23C6 FPGA chip.
Keywords: Egypt’s second Training and Research Reactor, Evolvable Hardware, Fault Tolerant, Virtual Reconfigurable Hardware,.