High Performance and Low-Power Full Adder
Mohammad Hassan Chamansara1, Ayat Akbari2, Hassan Taheri3, Abdolhamid Sohrabi4
1Mohammad Hasan Chamansara, Electronic engineering Department, Bushehr Branch Islamic Azad University, Bushehr, Iran.
2Ayat Akbari, Technical and vocational university, Bushehr Branch, Bushehr, Iran.
3Hassan Taheri, Electronic engineering Department, Bushehr Branch Islamic Azad University, Bushehr, Iran.
4Abdolhamid Sohrabi, Electronic engineering Department, Bushehr Branch Islamic Azad University, Bushehr, Iran.
Manuscript received on November 11, 2013. | Revised Manuscript received on November 15, 2013. | Manuscript published on November 25, 2013. | PP:5-8 | Volume-2 Issue-1, November 2013. | Retrieval Number: A0550112113/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers . Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (VTH) variations play on the reliability of a classical 28- transistor FA, and shows that reliability can be enhanced without increasing the occupied area, and while also reducing power consumption. An enabling transistor sizing scheme is used to improve on reliability without increasing power consumption (as reducing and limiting currents). The proposed FA in 16nm predictive technology model (PTM) is significantly more reliable (six orders of magnitude in case of Cout, and three orders of magnitude in case of Sum at 10% input variations) and dissipates 38× less than a classical FA, while being 6× slower.
Keywords: Full adder, CMOS, power, energy, reliability.