Design of Low Power Phase Frequency Detectors for Delay Locked Loop
Raj Nandini1, Himadri Singh Raghav2, B.P.Singh3
1Raj Nandini, ECE Department, Mody Institute of Technology and Science, Sikar, India.
2Himadri Singh Raghav ECE Department, Mody Institute of Technology and Science, Sikar, India .
3Prof.B.P.Singh ECE Department, Mody Institute of Technology and Science, Sikar, India
Manuscript received on March 11, 2013. | Revised Manuscript Received on March 12, 2013. | Manuscript published on March 25, 2013. | PP: 59-61 | Volume-1 Issue-5, March 2013. | Retrieval Number: E0229031513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A simple new Phase Frequency Detector design is presented in this paper. The PFD which helps Delay Locked Loop (DLL) to achieve simultaneous phase and frequency error detection is an indispensable block and plays an important role in improving the performance of the whole DLL system. Both conventional and improved PFDs are implemented using tanner 0.18 μm CMOS Process. The layouts are also designed using Tanner Tool. The maximum frequency of operation is 1 GHz when operating at 1.8V voltage supply. It can be used in DLL for high speed and low power consumption applications.
Keywords: CMOS Integrated Circuits, Delay Locked Loop, Phase Frequency Detector, Tanner