FPGA Implementation of Hybrid Cryptosystem
M. N. Praphul1, K. R. Nataraj2
1M.N Praphul. ECE, SJBIT, Bangalore, India.
2Dr K.R.Nataraj, HOD, ECE, SJBIT, Bangalore, India.
Manuscript received on June 11, 2013. | Revised Manuscript received on June 15, 2013. | Manuscript published on June 25, 2013. | PP: 14-19 | Volume-1 Issue-8, June 2013. | Retrieval Number: H0341061813/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With the development of Computer Network and Communication Technology, a great mass of data and information need to be exchanged by public communication networks. High efficiency and high safety of data transmission become much more important. There are several information encryption algorithms of which, Advanced Encryption Standard (AES) and Rivest Shamir Adleman (RSA) are widely used two algorithms of symmetric encryption technology and asymmetric encryption technology respectively. The existing symmetric scheme-AES algorithm provides high speed stream for large data and uses less amount of computer resources but induces less degree of security in large amount of data. The asymmetric cryptographic algorithm or a public key cryptographic algorithm-RSA is more secure comparatively, as it has two keys one for encryption and another one for decryption, but is much slower and uses a huge amount of computer resources. In order to cope up with these short comings, a proposal to use an improved version of the hybrid encryption scheme is done, which is a combination of Advanced Encryption Standard (AES) and Rivest Shamir Adleman (RSA) with cross encrypted keys for secure key exchange and hybrid encryption for enhanced cipher-text security. This system is implemented on Spartan 3 FPGA using VHDL as the programing language.Synthesizing and implementation of the code is carried out on Xilinx -Project Navigator, ISE 12.1i suite.
Keywords: Advanced Encryption Standard (AES), FPGA, hybrid encryption, Rivest Shamir Adleman (RSA),