Design & Study of a Low Power High Speed Full Adder using GDI Multiplexer
Gadi Appala Naidu1, Yelithoti Sravana Kumar2
1Gadi Appala Naidu, PG Scholar, Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam (A.P.), India.
2Yelithoti Sravana Kumar, Assistant Professor, Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam (A.P.), India.
Manuscript received on February 06, 2017. | Revised Manuscript received on February 15, 2017. | Manuscript published on February 25, 2017. | PP: 40-43 | Volume-4 Issue-8, February 2017. | Retrieval Number: H1154024817
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multiplexers. Full adder is a very common example of combinational circuits and is used widely in Application Specific Integrated Circuits (ASICs). It is always advantageous to have low power action for the sub components used in VLSI chips. The explored technique of realization achieves a low power high speed design for a widely used subcomponent- full adder. Simulated outcome using state-of-art simulation tool shows finer behavioral performance of the projected method over general CMOS based full adder. Power, speed and area comparison between conventional and proposed full adder is also presented.
Keywords: Low power full adder, 2-Transistor GDI MUX, ASIC (Application Specific Integrated Circuit), 12-TFA, CMOS (Complementary Metal Oxide Semiconductor.