Design & Simulation of CMOS Inverter at Nanoscale beyond 22nm
Adil Zaidi1, Kapil Garg2, Ankit Verma3, Ashish Raheja4
1Adil Zaidi Electronics & Communication, CET-IILM-AHL, Greater Noida, Uttar Pradesh, India.
2Kapil Garg, Electronics & Communication, CET-IILM-AHL, Greater Noida,, Uttar Pradesh, India.
3Ankit Verma, Electronics & Communication, CET-IILM-AHL, Greater Noida,, Uttar Pradesh, India.
4Ashish Raheja, Electronics & Communication, CET-IILM-AHL, Greater Noida,, Uttar Pradesh, India.
Manuscript received on March 11, 2013. | Revised Manuscript Received on March 12, 2013. | Manuscript published on March 25, 2013. | PP: 83-87 | Volume-1 Issue-5, March 2013. | Retrieval Number: E0220031513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power and area are the two major concerns in design of any digital circuit. At present scenario low power device design and its implementation have got a significant role in the field of nano electronics. This paper investigates the applications of CMOS technology in the nanometer regime beyond 22 nm channel length where the relative study of average power dissipation of CMOS inverter is found in nano Watts. The simulation results are taken at different channel length (16nm 22nm, 32nm, 45nm) using CMOS technology with the help of (H-spice) simulation tool. The results are analyzed at different supply voltages keeping constant load capacitance (C load =1fF) apart from this, values of various internal parameters of CMOS Inverter at different channel length are calculated.
Keywords: Nano-electronics, UDSM (Ultra Deep Sub-Micron) Technology, CMOS, and Scaling.