VLSI Implementation of DES & TDES Algorithm with Cipher Block Concept
Chethan Kumar K. V.1, S. Sujatha2
1Chethan Kumar K V, He received his Bachelor of Engineering Degree from M.S Engineering College, and he is pursuing his Masters Degree from Bangalore Institute of Technology. India.
2S Sujatha, Associate Professor, Dept of Electronics and Communication Engineering, Bangalore Institute of Technology, Bengaluru, Karnataka, India.
Manuscript received on May 15, 2014. | Revised Manuscript received on May 18, 2014. | Manuscript published on May 25, 2014. | PP:10-15 | Volume-2 Issue-7, May 2014. | Retrieval Number: F0721042614/2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents FPGA implementation of the DES and Triple-DES with improved security against power analysis attacks. This is programmed in verilog. DES & TDES is basically used in various cryptographic applications and wireless protocol security layers. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. Triple DES was the answer to many of the shortcomings of DES. Since it is based on the DES algorithm, it is very easy to modify existing software to use Triple DES. It also has the advantage of proven reliability and a longer key length that eliminates many of the shortcut attacks that can be used to reduce the amount of time it takes to break DES. However, even this more powerful version of DES may not be strong enough to protect data for very much longer. The DES algorithm itself has become obsolete and is in need of replacement.DES encrypts data in 64-bit and it is a symmetric algorithm. The key length is 56-bits. This paper covers DES and Triple DES algorithm with Cipher Block concept, simulation results, basic FPGA technology and the implementation details of the proposed DES and Triple DES architecture. Register transfer level (RTL) of DES and Triple DES algorithm is designed, simulated and implemented separately using Verilog in different FPGA devices including Cyclone II, Spartan 3, Vertex 5 and Vertex E series FPGAs. The results from the comparison with existing implementations show that the proposed design was efficient in all aspects..
Keywords: DES, FPGA, TDES, RTL, Verilog