Design of Low Glitch Dynamic Phase Detector for Delay Locked Loop
Shirish Tripathi

Shirish Tripathi, Electronics & Communication Engineering Department, Pranveer Singh Institute of Technology, Kanpur, India.
Manuscript received on June 11, 2013. | Revised Manuscript received on June 15, 2013. | Manuscript published on June 25, 2013. | PP: 1-4 | Volume-1 Issue-8, June 2013. | Retrieval Number: H0333061813/2013©BEIESP

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Abstract: A simple Low Glitch Dynamic Phase Detector is proposed in this paper. The Dynamic PD helps Delay Locked Loop to achieve phase error detection in high speed synchronous circuits and plays an important role in improving the performance of the complete DLL block. A high speed, low glitch phase detector is proposed in 180 nm technology with VDD=1.8V in Cadence Schematic Composer for schematic capture, analog artist (Spectre) Tool for simulations and Virtuoso for layouts. The proposed PD is having a better phase sensitivity, phase noise and less power dissipation. Simulation results show that the proposed PD has low glitch as compared to conventional PD based on D flip-flop. So, the speed of the proposed Dynamic PD is also high.
Keywords: Delay Locked Loop, Phase Detector, Cadence, CMOS Technology.