Design and Synthesis of Reversible Fault Tolerant Carry Skip Adder/Subtractor
Prashanth. N. G1, Manojkumar. S. B2, Balaji. B. S3, Naveena Pai G4, Havyas. V. B5
1Prashanth.N.G, PG Student, VLSI Design and Embedded System, B.G.S. Institute of Technology, B.G.Nagar, Mandya-571448, Karnataka, India.
2Manojkumar.S.B, Assistant Professor, Department of Electronics and Communication Engineering, B.G.S. Institute of Technology, B.G.Nagar, Mandya-571448, Karnataka, India.
3Balaji. B.S, Assistant Professor, Department of Electronics and Communication Engineering, B.G.S. Institute of Technology, B.G. Nagar, Mandya-571448, Karnataka, India.
4Naveena Pai G, PG Student, VLSI Design and Embedded System, B.G.S. Institute of Technology, B.G. Nagar, Mandya-571448, Karnataka, India.
5Havyas. V.B, PG Student, VLSI Design and Embedded System, B.G.S. Institute of Technology, B.G.Nagar, Mandya-571448, Karnataka, India.
Manuscript received on June 11, 2013. | Revised Manuscript received on June 15, 2013. | Manuscript published on June 25, 2013. | PP: 55-58 | Volume-1 Issue-8, June 2013. | Retrieval Number: H0351061813/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Reversible logic will be having more demand in future computation technology because of its zero power dissipation under ideal conditions. This paper proposes the fault tolerant carry skip adder/subtractor by using parity preserving reversible logic gates. According to the control logic input the proposed design can works as a carry skip adder or carry skip subtractor.
Keywords: Reversible Logic Gates, Parity Preserving reversible Logic Gates, Full Adder/Subtractor, Parallel Adder/Subtractor, Carry Skip Adder/Subtractor