Design of AXI4 Protocol Checker for SoC Integration
Veena Abraham1, Soumen Basak2, Sabi S3

1Veena Abraham, Department of Electronic and Communication, Sree Buddha College of Engineering, Kerala.
2Soumen Basak, Chief Technology Officer, DSipher Design Solutions Pvt. Ltd, Bangalore.
3Sabi S, Department of Electronic and Communication, Sree Buddha College of Engineering, Kerala..

Manuscript received on June 11, 2013. | Revised Manuscript received on June 15, 2013. | Manuscript published on June 25, 2013. | PP: 59-65 | Volume-1 Issue-8, June 2013. | Retrieval Number: H0356061813/2013©BEIESP

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Abstract: System-on-a-Chip (SoC) design has become more and more complex because Intellectual Property (IP) core with different functions are integrated within a single chip. Each IPs have completed design and verification but the integration of all IPs may not work together. The bus-based architecture has become the major integration methodology for implementing a SoC. The main issue is to ensure that the IP works correctly after integrating to the corresponding bus architecture. Advanced extensible interface 4 (AXI4) is an on chip bus architecture introduced by ARM to interact with its peripherals. A synthesizable AXI4 protocol checker which contains a set of rules to check on-chip communication properties accuracy is proposed to ensure proper SoC integration. A prototype of AXI4 Master and AXI Slave is also designed to generate the AXI4 signals. The protocol checker will continuously monitor the signals from AXI4 Master and AXI4 Slave to check whether any rule is broken or not. The proposed AXI4 protocol checker will check both the Write Channel and Read Channel transactions. As the AXI4 checker is synthesizable it can be used in FPGA (Field Programmable Gate Array) and Emulation where functional checks are difficult to detect and pin point. The AXI4 Master, AXI Slave and AXI4 protocol checker have been modeled using Verilog and implemented on Digilent Basys2 Spartan 3E FPGA board.
Keywords: System on a Chip, AXI4 protocol, Intellectual Property cor, Write Channel, Read channel..