Design and Operation of 4X1 Low Power Multiplexer using Different Logics
Yalla Hareesh1, Yelithoti Sravana Kumar2
1Yalla Hareesh, PG Scholar, Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam (A.P.), India.
2Yelithoti Sravana Kumar, Assistant Professor, Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam (A.P.), India.
Manuscript received on February 06, 2017. | Revised Manuscript received on February 15, 2017. | Manuscript published on February 25, 2017. | PP: 36-39 | Volume-4 Issue-8, February 2017. | Retrieval Number: H1153024817
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power and high speed digital circuits are basic needs for any of digital circuit. Multiplexer is a basic circuit for any digital circuit. In this paper, different techniques of multiplexer designs like Complementary CMOS, Transmission gate, Pass transistor logic, Dual Pass transistor logic styles and Gate Diffusion Input has been introduced and their comparison on the basis of power, delay and Area (number of transistor) is done. A low power Multiplexer has been introduced which consumes least power as compare to above mentioned logic but have more delay as compare to other ,On the basis of these analyses it is concluded that proposed multiplexer is better technique for designing an low power low area Multiplexer design but it has high delay as compare to other Multiplexer.
Keywords: CMOS, DPTL, PT, TG, GDI.